Chinese university builds 3D chip design tool tailored to Huawei's 'LogicFolding' architecture — 3D design delivers increased performance and better thermal management

Peking University’s School of Integrated Circuits unveiled a prototype EDA tool for Huawei’s LogicFolding 3D chip architecture.

The tool uses a true-3D workflow that treats stacked layers as one design space, rather than separate planes.

Early tests on open-source circuits showed about 30% less internal wiring, along with better speed and heat handling.

The announcement came after Huawei presented LogicFolding at ISCAS 2026, saying it could reach advanced-node-like density without EUV lithography.

The effort highlights China’s push to build domestic EDA software for next-gen chips and cut reliance on Western design tools.