Aegis – open-source FPGA silicon | Hacker News
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2 min readKey summary
The Aegis open-source FPGA project includes a SerDes block that wraps PDK components.
The SerDes appears to use a 50 MHz internal clock with 8x oversampling, implying a 400 MHz effective rate.
Contributors say the design is useful for a first silicon spin, though the DSP tile's operation is set by bitstream rather than fabric, complicating accumulator reset.
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