TSMC is developing an advanced AI semiconductor packaging technology it internally calls "quasi-EMIB," possibly similar to Intel's Embedded Multi-die Interconnect Bridge technology

TSMC is reportedly developing a new 2.5D packaging technology internally dubbed “quasi-EMIB.”

The design reportedly borrows from Intel’s EMIB by using localized silicon bridge-style interconnects to link chiplets.

TSMC is said to be working with substrate maker Kinsus, potentially reducing reliance on larger CoWoS-style interposers.

The effort appears aimed at easing CoWoS capacity constraints and meeting surging AI/HPC packaging demand.

If successful, it could offer a cheaper, more scalable chiplet interconnect option and intensify competition with Intel in advanced packaging.