I designed a nibble-oriented CPU in Verilog to build a scientific calculator

An engineer built a nibble-oriented Verilog CPU tailored to scientific-calculator workloads, using 4-bit-wide, nibble-addressable memory for BCD arithmetic.

The design adds trig functions with CORDIC and includes a custom assembler plus debugging tools to make development practical.

The system was deployed across simulation, desktop, browser, and custom hardware, turning the calculator into a full end-to-end platform.

The project highlights how matching CPU design to decimal calculator needs can simplify arithmetic and enable a from-scratch calculator stack.