Sub-1nm Process Technology Won’t Arrive Until 2034, Logic Roadmap Highlights 2D FETs for 0.2nm and Sub-0.2nm Nodes by 2043–2046

IMEC’s new logic roadmap extends semiconductor scaling through the 2030s and 2040s.

It expects nanosheet-based nodes to continue into the early 2030s, with sub-1nm CFET nodes starting around 2034.

The roadmap then points to 2D FET technologies reaching 0.2nm and below in 2043–2046.

The outlook suggests continued gains in performance and density, even as costs rise and advanced packaging becomes more important.