Show HN: Auto-Architecture: Karpathy's Loop, pointed at a CPU | Hacker News

A Show HN post describes a Karpathy-style auto-architecture experiment that iteratively optimizes a CPU on a Gowin FPGA.

The fitness loop uses CoreMark and clock frequency, with nextpnr and timing analysis guiding design choices.

The author says the chip’s weak carry chain, routing, and register-file behavior limit gains, so most improvements come from working around hardware constraints.

The post underscores how FPGA limitations and tool accuracy can shape CPU performance and future architecture-reversal work.