Inside Google's TPU V8 strategy, delivering two chips for two crucial tasks at incredible scale — network scales up to 1 million TPUs per cluster, an advantage over Nvidia AI accelerators

Google unveiled eighth-generation TPUs with a split strategy: TPU 8t for large-scale training and TPU 8i for low-latency inference and reasoning.

It is the first time Google has used two TPU designs in one generation, signaling a clearer workload-specific approach to AI chips.

The new chips use TSMC’s N3 process and HBM3E memory, with MediaTek joining Broadcom as a design partner.

Google also emphasized larger cluster-scale infrastructure, including superpods and Virgo Network, to link huge numbers of TPUs across data centers.

The strategy shifts the battle with Nvidia and AMD toward networked scale and system design, not just raw chip performance.