Monolithic 3D silicon chips achieve near-perfect yields at low temperatures

University of Illinois Urbana-Champaign researchers developed a low-temperature process to stack ultrathin single-crystal silicon layers onto finished circuits.

The method works below 200°C and enabled a three-layer monolithic 3D chip with 625 transistors per layer.

The team reported 98% to 100% yields and demonstrated functioning logic and memory devices, including junctionless transistors and SRAM.

The approach could increase computing density and efficiency without relying only on transistor shrinking, supporting future semiconductor scaling.