Moore's law is hitting a wall, so researchers are stacking silicon chip layers instead of shrinking them

University of Illinois researchers led by Qing Cao demonstrated working silicon circuits built from ultrathin single-crystal nanomembranes transferred onto a wafer.

The low-temperature process enables monolithic 3D chip stacking, letting logic and memory be placed vertically without damaging earlier layers.

The goal is to boost compute density and bandwidth by using the third dimension instead of relying only on smaller transistors.

As Moore’s law slows, this approach could extend chip performance gains through better interconnects and denser integration.